application note AN129-1 AN129 what is mps e2? by application staff, november 1999 introduction the x84256 mps ? e 2 (microprocessor compatible serial e2prom) is a 256k-bit nonvolatile serial memory organized as 32k x 8. however, due to the sequential nature of the device, the use of consecutive reads or writes to the device also allows it to be used in 16-bit or 32-bit environments. this device supports an 64-byte page with a typical nonvolatile write cycle time of 5ms. additionally, there is a write protect pin (wp) to disable all nonvolatile writes to the device. the unique feature of this device is its ability to directly interface with a parallel data bus without glue logic. its small size, low power, and low cost make it an ideal alter- native to parallel access nonvolatile memory devices. system designers currently using parallel access devices to hold con?guration data (e.g. motherboards, add-on cards, pcmcia cards, plug and play cards, data record- ing systems, etc...) will especially bene?t from the features of the x84256. this cmos device utilizes xicors proprietary direct write ? e 2 prom cell technology which allows for an endurance of at least 1,000,000 write cycles per byte and a minimum data retention of 100 years. x84256 data bus cycles an understanding of how the mps e 2 serial interface works can be gained from the included bus cycle dia- grams. the system designer accesses the x84256 using standard read or write activity on a parallel data bus. the interface is accomplished by directly connecting a sin- gle i/o pin from the data bus, as well as the we and oe signals generated by the system processor and an address decoded ce . when the x84256 is selected, the device will interpret each read or write on the data bus as a single bit in the serial interface protocol. since the device is in standby mode when ce is high, the serial interface scheme is fully static and can be interrupted at any time to perform other bus activities. at a later time, communications with the device can be resumed from the point when the communications were interrupted. figure 1. x84256 mps ? e2 block diagram ce i/o h.v. generat ion timing & control eeprom array 32k x 8 command decode and control logic x dec ydecode data reg ister wp oe we direct write and mps are trademarks of xicor, inc.
xicor application note AN129-2 AN129 in order to complete the interface, there are two additional unique sequences to reset the device and to initiate a nonvol- atile write cycle. a reset condition is recognized by the x84256 whenever the system processor issues the following sequence: read, write a zero, and read. this 3-bus cycle sequence is used to initialize the part before a read or write sequence or to interrupt a sequence already in progress. an initiate nonvolatile write cycle condition is recognized by the x84256 whenever the system processor issues the following sequence: read, write a one, and read. this sequence is used to begin an internal write cycle after data has been loaded into the device. an additional feature of the device is the ability to determine the early completion of an internal nonvolatile write cycle. this can be accom- plished by polling the level of the i/o pin during a nonvolatile write cycle. when the i/o pin can be read as a logic high, then the cycle is complete and the part is again able to interact within the system. the x84256 read sequences should usually be initiated with a reset sequence, followed by 16 consecutive writes to the device without a read. these 16-bits are for the initial memory address to be accesssed (msb ?rst). figure 2. x84256 read cycle ce oe we i/o (in) "0" reset when accessing: x84256 array: a15=0 load address read data a10 a11 a12 a13 a14 a15 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 i/o (out) t) d7 d6 d5 d4 d3 d2 d1 d0
xicor application note AN129-3 AN129 at this point, the system processor can sequentially read any number of bits from the device beginning at the initial address. write sequences follow the same format. typically, the x84256 can be completely rewritten using page writes in less than 325ms when the technique of i/o polling for the early completion of each nonvolatile write cycle is used. figure 3. x84256 write cycle ce oe we i/o(in) "0" "0" "1" reset load address load data a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 i/o(out) start nonvolatile write when accessing: x84256 array: a15=0 a10 a11 a12 a13 a14 a15 a9
xicor application note AN129-4 AN129 interfacing to the x84256 the x84256 is designed so that it is compatible with systems using either ce controlled write cycles (e.g. motorola processors) or we controlled write cycles (e.g. intel processors). the following circuits show how simply the interfacing can be accomplished for different environments, such as the 68000, 80x86, 8051 microcontrollers, and tms320 dsp processors. figure 4. ce controlled write cycle environment (68000) clk c2 ip l0 j12 ip l1 j13 ip l2 h 1 2 av ec h2 bgack a1 br b3 be rr j2 cdis h1 dsack0 h3 dsack1 j1 d0 k13 d1 k12 d2 l13 d3 l12 d4 m13 d5 m1 2 d6 m11 d7 l10 d8 n12 d9 n11 d10 m10 d11 l9 d12 n10 d13 m9 d14 n9 d15 l8 d16 m7 d17 n6 d18 m6 d19 l6 d20 n5 d21 m5 d22 n4 d23 l5 d24 m4 d25 n3 d26 m3 d27 l4 d28 n2 d29 m2 d30 l3 d31 n1 a0 c4 a1 a2 a2 e12 a3 d13 a4 d12 a5 c13 a6 b1 3 a7 c12 a8 a1 3 a9 c11 a10 b1 2 a11 a1 2 a12 c10 a13 b11 a14 a11 a15 b1 0 a16 c9 a17 c8 a18 b8 a19 a8 a20 b7 a21 c7 a22 a7 a23 a6 a24 b6 a25 c6 a26 a5 a27 b5 a28 a4 a29 c5 a30 b4 a31 a3 ipend f13 bg b2 fc0 e1 fc1 f3 fc2 f2 siz0 f1 siz1 g2 dben g3 ecs g1 ocs e1 rmc e2 as l1 ds m1 rw l2 halt k2 eset c1 u2 68020 1 3 data bus address bus memory segment 32 address decode i/o 2 wp 3 oe 6 we 5 ce 1 u1 x84256 write protect 12 3 u4a 74h c00 45 6 u4b 74 hc 00 memory read memory write 1 2 u3a 74h c04 3 4 u3b 74hc 04
xicor application note AN129-5 AN129 figure 5. we controlled write cycle environment (80x86) although the device is speci?ed as requiring 100ns read cycle (trc) and write cycle (twc) times, there should be no problem interfacing to typical high speed busses. these cycle times are sums of the low pulse (oe or we ) and the high phase required before the next low pulse. as long as the low pulse minimum lengths are satis?ed according to the bus timings of the x84256, then in software, a designer can accomodate the minimum cycle length requirement by issuing nop instructions (or any instructions that will take suf?cient time to execute). address/data bus ad0 16 ad1 15 ad2 14 ad3 13 ad4 12 ad5 11 ad6 10 ad7 9 ad8 8 ad9 7 ad10 6 ad11 5 ad12 4 ad13 3 ad14 2 ad15 39 a16/s3 38 a1 7 /s4 37 a1 8 /s5 36 a19/s6 35 bhe/s7 34 den 26 dt/r 27 m/io 28 rd 3 2 wr 29 ale 25 inta 24 mn 33 read y 22 clk 19 reset 21 intr 18 hlda 30 hold 31 nmi 17 test 23 8086 ( min m ode ) 20 1 address decode i/o 2 wp 3 oe 6 we 5 ce 1 u1 x84256 write protect
xicor application note AN129-6 AN129 figure 6. dsp systems (tms320) figure 7. microcontroller systems (8051) address bus data bus d0 30 d1 29 d2 28 d3 27 d4 26 d5 25 d6 24 d7 23 d8 13 d9 12 d10 11 d11 10 d12 9 d13 8 d14 7 d15 6 a 0 5 5 a 1 5 6 a 2 5 7 a 3 5 8 a 4 5 9 a 5 6 0 a 6 6 1 a 7 6 2 a 8 6 3 a 9 6 4 a 1 0 7 2 a 1 1 7 3 a 1 2 7 4 a 1 3 7 5 a 1 4 7 6 a 1 5 7 7 x2/clkin1 96 clkin2 95 clkmd1 71 clkmd2 103 clkou t1 110 mp/mc 5 trst 2 iaq 1 bio 130 hold 129 rs 127 emu1/off 11 9 iack 112 msc 111 holda 108 br 94 st rb 9 3 r/w 9 2 ps 9 1 is 9 0 ds 8 9 we 8 3 rd 8 2 nmi 42 int1 38 int2 39 in t3 40 int4 41 dr 43 tdr 44 fsr 45 tms 31 t c k 3 4 t d i 6 7 t d o 1 0 0 t d x 1 0 7 t o u t 1 2 2 r e a d y 1 2 8 t f s r / t a d d 1 2 5 t f s x / t f r m 1 0 5 x f 1 0 9 d x 1 0 6 x 1 9 7 f s x 1 0 4 clkr 46 tclkr 126 tclkx 123 clkx 124 emu0 118 u2 tms320c5x address decode 16 1 write protect i/o 2 wp 3 oe 6 we 5 ce 1 u1 x84256 ea/vp 31 x1 19 x2 18 reset 9 int0 1 2 int1 13 t0 14 t1 1 5 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd 17 wr 16 ps en 29 ale/p 30 txd 11 rxd 10 u2 8051 16 1 address/data bus i/o 2 wp 3 oe 6 we 5 ce 1 u1 x84256 address decode wr ite protect
xicor application note AN129-7 AN129 the x84256 can also be an effective alternative for systems that otherwise have serial data port capabilities. for many microcontrollers, a designer is limited to only a few bit, addressable i/o port pins. instead of using one of these pins strictly for e 2 prom communications, a designer can use the x84256. a commonly encountered circuit uses 2 i/o port pins of an 8051 microcontroller to interface to an i 2 c e 2 prom. one previous circuit example shows how the x84256 frees up these port pins. *******************************************************************************************************/ /* /* xicor x84256 mps e2 /* /* the following c subroutines are provided to interface with an x84256 that is memory mapped into the /* i/o space of an ibm pc or compatible environment. with these subroutines, a designer can read multiple /* data bytes from the x84256 by using the simple function call: /* /* read_x84256(int no_bytes,int addr,int io_port,unsigned char *bytes) /* /* any number of bytes (no_bytes) can be read sequentially from the starting address (addr) of the x84256 /* mapped into a given i/o address (io_port). the results are passed back sequentially to a series of /* system locations pointed to by (bytes). care should be taken to provide enough locations for each data /* byte read. additionally, either a byte write or page write to the x84256 can be initiated with the /* following call: /* /* write_x84256(int no_bytes,int addr,int io_port,unsigned char *bytes) /* /* up to 8 bytes (as specified by no_bytes) can be written to the x84256 at an i/o address (io_port) /* beginning at a memory address (addr). sending more than 8 bytes will cause a "wrap-around" of data on /* the chosen page. the data to be written is contained in an array (pointed to by *bytes). these rou /* tines can be appended to other ansi c code with the following (or similar) compiler directive: /* /* #include "c:\xicor.c " /* /* note that the source code should have an #include statement since the code (xicor.c) needs /* access to the inportb() and outportb() functions. /* ghc iv /******************************************************************************************************/ /******************************************************************************************/ /* sends reset sequence to the x84256 at io_port /******************************************************************************************/ void x84reset(int io_port) { inportb(io_port); /* read bit from io_port */ outportb(io_port,0x00); /* write a low bit to io_port */ inportb(io_port); /* read bit from io_port */ } /******************************************************************************************/ /* writes a one to the x84256 at io_port /******************************************************************************************/ void x84write_one(int io_port) { outportb(io_port,0xff); /* write a high bit to io_port */ } /******************************************************************************************/ /* writes a zero to the x84256 at io_port /******************************************************************************************/ void x84write_zero(int io_port) { outportb(io_port,0x00); /* write a low bit to io_port*/ } /******************************************************************************************/ /* reads a bit from the x84256 at io_port /******************************************************************************************/ int x84read(int io_port) { int bit_val; bit_val = inportb(io_port) & 1; /* read bit d0 from io_port */ return(bit_val); /* return bit value to calling routine */ } /******************************************************************************************/ /* polls for the early completion of a nonvolatile write cycle in the x84256 at /* io_port /******************************************************************************************/ void x84poll(int io_port) { int bit_temp; do { bit_temp=x84read(io_port); /* continuously read bits until the bit is high */ } while (bit_temp == 0);
xicor application note AN129-8 AN129 } /******************************************************************************************/ /* initiates and completes a nonvolatile write cycle in the x84256 at io_port /******************************************************************************************/ void x84write_start(int io_port) { x84read(io_port); /* read bit from io_port */ x84write_one(io_port); /* write a low bit to io_port */ x84read(io_port); /* read bit from io_port */ x84poll(io_port); /* poll the i/o pin for completion of write cycle */ } /******************************************************************************************/ /* sends all 16 required address bits, including don't cares, to the x84256 at /* io_port /******************************************************************************************/ void x84addr_send(int dont_care,int io_port,int addr) { int addr_bit,mask_addr,addr_temp; for (addr_bit = 0; addr_bit < dont_care; addr_bit++) { x84write_zero(io_port); /* loop and send don't cares */ } mask_addr = 256; /* bit mask to isolate address msb */ for (addr_bit = 0; addr_bit < (16-dont_care); addr_bit++) { /* loop through all 9 address bits */ addr_temp = addr & mask_addr; /* mask to determine next required address bit */ if (addr_temp == 0) /* if address bit is low, then ... */ x84write_zero(io_port); /* write a low bit to io_port */ else x84write_one(io_port); /* otherwise, write a high bit to io_port */ mask_addr = mask_addr >> 1; /* shift bit mask right to get next bit */ } } /******************************************************************************************/ /* sends all 8 data bits to the x84256 at io_port /******************************************************************************************/ void x84data_send(int io_port,int data) { int mask_data,data_temp,data_bit; mask_data = 128; /* bit mask to isolate data msb */ for (data_bit = 1; data_bit < 9; data_bit++) {/* loop through all 8 data bits */ data_temp = data & mask_data; /* mask to determine next required data bit */ if (data_temp == 0) /* if data bit is low, then ... */ x84write_zero(io_port); /* write a low bit to io_port */ else x84write_one(io_port); /* otherwise, write a high bit to io_port */ mask_data = mask_data >> 1; /* shift bit mask right to get next bit */ } } /******************************************************************************************/ /* reads 8 data bits from the x84256 at io_port and reconstructs the databyte /******************************************************************************************/ int x84data_get(int io_port) { int n,bit_temp[9]; bit_temp[0]=0; /* clear array position 0, resetting previous sum */ for (n=1;n<9;n++) { /* loop through 8 data bits */ bit_temp[n] = x84read(io_port)+2*bit_temp[n-1]; /* at the current position, shift the previous sum of */ /* data bits left, read the next bit, add it to previous */ } /* sum, and store the result */ return(bit_temp[8]); /* return the data byte value to the calling routine */ } /******************************************************************************************/ /* general read master routine that is called by the user in order to read a /* number of bytes from the x84256 at io_port /******************************************************************************************/ void read_x84256(int no_bytes,int addr,int io_port,unsigned char *bytes) { int n; x84reset(io_port); /* reset the x84256 */ x84addr_send(7,io_port,addr); /* send the address bits (don't cares & addr) */ for (n=0;n xicor application note AN129-9 AN129 /* number of bytes to the x84256 at io_port /******************************************************************************************/ void write_x84256(int no_bytes,int addr,int io_port,unsigned char *bytes) { int n; x84reset(io_port); /* reset the x84256 */ x84addr_send(7,io_port,addr); /* send the address bits (7 don't cares & addr) */ for(n=0;n #include unsigned char send_buffer[8], receive_buffer[512]; /* maximum buffer sizes needed for x84256 protocol */ . . . main () { write_x84256(4,0,0x303,&send_buffer); read_x84256(22,0x1f,0x303,&receive_buffer); }
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